1. Field of the Invention
The present invention relates to a semiconductor test apparatus for testing an analog circuit (e.g., an analog-to-digital converter or a digital-to-analog converter) which is one of LSIs to be tested [hereinafter called xe2x80x9cDUTxe2x80x9d (device under test)] by an LSI test apparatus (hereinafter called xe2x80x9ctesterxe2x80x9d), as well as to a method of testing a semiconductor device using the semiconductor test apparatus.
2. Background Art
Recently, in relation to a system LSI (embodied in a one-chip LSI consisting of a plurality of functionally-systematized circuit modules or embodied in a chip set LSI), combination of digital and analog circuits (i.e., a system LSI handling a mixed signal), having high-performance and precision, has been rapidly pursued. In order to cope with such a tendency, tester manufacturers have provided testers compatible with a semiconductor integrated circuit using a mixed signal. A tester compatible with a semiconductor integrated circuit using a mixed signal has high performance specifications and inevitably becomes expensive. For this reason, one proposed resolution is recycling an existing low-speed, low-precision tester (e.g., a tester for a logic LSI), to thereby avoid a hike in the price of a tester.
A big problem with such a test apparatus lies in a characteristic test for a converter circuit for converting a digital signal into an analog signal (digital-to-analog converter, hereinafter called a xe2x80x9cDACxe2x80x9d) as well as in a characteristic test for a converter circuit for converting an analog signal into a digital signal (hereinafter called an xe2x80x9cADCxe2x80x9d) In a testing environment of a general tester, connection jigs for connecting a tester with a DUT, such as a plurality of DUT circuit boards (simply called xe2x80x9cDUT boardsxe2x80x9d) and cables, are provided at a plurality of points along a measurement path extending from measurement equipment provided in the tester to a DUT. Further, the measurement path is long and accounts for occurrence of noise and a drop in measurement accuracy. A limitation is imposed on the speed of a low-speed tester, and hence the low-speed tester cannot conduct a test at a real operating speed, thereby posing a fear of an increase in a time required for conducting mass-production testing of a system LSI.
FIG. 6 is a block diagram showing a BOST (Built-off-self-test) device of a related-art semiconductor test apparatus which has been conceived for shortening a test time according to a method of testing a DAC of a DUT and which employs a technique for conducting a test through use of an external ADC disposed in the vicinity of a DUT.
As shown in the drawing, reference numeral 1 designates a tester; 2 designates a DUT; 3 designates a digital-to-analog converter section of the DUT 2; 4 designates an output section of the DUT 2; 5 designates a CPU of the DUT 2; 6 designates an analog-to-digital converter section; 7 designates a digital signal entered by way of the tester 1; 8 designates an analog signal produced through digital-to-analog conversion; 9 designates a digital signal produced through analog-to-digital conversion; 10 designates a CPU of the tester 1; 11 designates RAM; 12 designates a signal for controlling input/output operations of the RAM 11; and 13 designates a digital signal output from the RAM 11.
The operation of the BOST device will now be described.
The digital signal 7 entered by way of the tester 1 is converted into an analog signal by means of the digital-to-analog converter section 3 of the DUT 2. The thus-converted signal is further subjected to analog-to-digital conversion in the analog-to-digital converter 6, and the thus-converted data are stored in the RAM 11. After all these operations have been performed, the data stored in the RAM 11 are output. The thus-output data and the data input to the digital-to-analog converter section 3 of the DUT 2 are compared by the tester 1, thus making an evaluation of the DAC.
FIG. 7 is a block diagram showing a BOST device of a related-art semiconductor test apparatus which has been conceived for shortening a test time according to a method of testing an ADC of a DUT and which employs a technique for conducting a test through use of an external DAC disposed in the vicinity of a DUT. In FIG. 7, elements which are identical with those shown in FIG. 6 are as signed the same reference numerals, and repeated explanations thereof are omitted.
As shown in FIG. 7, reference numeral 14 designates a digital-to-analog converter; 15 designates a DUT; 16 designates an analog-to-digital converter section of the DUT 15; 17 designates an output section of the DUT 15; and 18 designates a CPU of the DUT 15.
The operation of the BOST device will now be described.
The digital signal 7 entered by way of the tester 1 is subjected to digital-to-analog conversion in the digital-to-analog converter 14, and the thus-converted signal is further subjected to analog-to-digital conversion in the analog-to-digital conversion section 16 of the DUT 15. Further the thus-converted data are stored in the RAM 11. After all these operations have been performed, the data stored in the RAM 11 are output. The thus-output data and the data input to the digital-to-analog converter 14 are compared by the tester 1, thus making an evaluation of the ADC.
The related-art semiconductor test apparatus shown in FIG. 6 suffers the following problems.
All data, addresses, and control signals stored in measured data storage memory; i.e., RAM, connected to an external ADC; i.e., an analog-to-digital converter,. must be supplied from a tester [a CPU and a timing pattern generator (TPG)]. The majority of pin electronics provided on a tester are occupied for testing a single ADC, thus imposing limitations on simultaneous measurement of a plurality of ADCs. Test results are evaluated after all tests have been completed. Hence, an effect of shortening a time required for effecting a real test is small. Further, measured data must be uploaded to a CPU of the tester, thus resulting in a chance of an increase arising in a processing time including communications time. Further, the related-art semiconductor test apparatus has failed to describe a control method and procedures and is devoid of specificity of a method of shortening a test time.
The related-art semiconductor test apparatus shown in FIG. 7 suffers the same problem as that encountered by the related-art test apparatus shown in FIG. 6.
The present invention has been conceived to solve the problems set forth and is aimed at providing a semiconductor test apparatus which is susceptible of simultaneously measuring a plurality of DUTs, enables shortening of a real test time, and obviates a necessity for uploading measured data to a CPU of the tester, as well as providing a method of testing a semiconductor device using the semiconductor test apparatus. According to one aspect of the present invention, an external test ancillary device which analyzes measured information output from a circuit under test and transmits a result to a semiconductor test apparatus, comprises a input data generator for generating data. Further the device comprises a first data converter for converting the data output from the input data generator from one signal scheme into another signal scheme. Further the device comprises a second data converter for converting input data from another signal scheme into one signal scheme. Further the device comprises a loopback line for supplying data output from the first data converter to the second data converter in the device. Further the device comprises a self-diagnostic section for performing a self-diagnostic operation on the basis of data output from the second data converter.
Other and further objects, features and advantages of the invention will appear more fully from the following description.